Tag Archives: Non-Transparent Sharing of Microarchitectural Resources

CWE-1303 – Non-Transparent Sharing of Microarchitectural Resources

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Description

Hardware structures shared across execution contexts (e.g., caches and branch predictors) can violate the expected architecture isolation between contexts.

Modes of Introduction:

– Architecture and Design

 

 

Related Weaknesses

CWE-1189
CWE-203

 

Consequences

Confidentiality: Read Application Data, Read Memory

Microarchitectural side-channels have been used to leak specific information such as cryptographic keys, and Address Space Layout Randomization (ALSR) offsets as well as arbitrary memory.

 

Potential Mitigations

Phase: Architecture and Design

Description: 

Microarchitectural covert channels can be addressed using a mixture of hardware and software mitigation techniques. These include partitioned caches, new barrier and flush instructions, and disabling high resolution performance counters and timers.

Phase: Requirements

Description: 

Microarchitectural covert channels can be addressed using a mixture of hardware and software mitigation techniques. These include partitioned caches, new barrier and flush instructions, and disabling high resolution performance counters and timers.

CVE References