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Description
Signals between a hardware IP and the parent system design are incorrectly connected causing security risks.
Modes of Introduction:
– Implementation
Related Weaknesses
Consequences
Confidentiality, Integrity, Availability: Varies by Context
Potential Mitigations
Phase: Testing
Description:
System-level verification may be used to ensure that components are correctly connected and that design security requirements are not violated due to interactions between various IP blocks.