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Description
Specific combinations of processor instructions lead to undesirable behavior such as locking the processor until a hard reset performed.
Modes of Introduction:
– Architecture and Design
Related Weaknesses
Consequences
Integrity, Availability: Varies by Context
Potential Mitigations
Phase: Testing
Description:
Implement a rigorous testing strategy that incorporates randomization to explore instruction sequences that are unlikely to appear in normal workloads in order to identify halt and catch fire instruction sequences.
Phase: Patching and Maintenance
Description:
Patch operating system to avoid running Halt and Catch Fire type sequences or to mitigate the damage caused by unexpected behavior. See [REF-1108].
CVE References
- CVE-1999-1476
- A bug in some Intel Pentium processors allow DoS (hang) via an invalid “CMPXCHG8B” instruction, causing a deadlock