Description
The chip does not implement or does not correctly perform access control to check whether users are authorized to access internal registers and test modes through the physical debug/test interface.
Modes of Introduction:
– Architecture and Design
Related Weaknesses
Consequences
Confidentiality: Read Application Data
Confidentiality: Read Memory
Authorization: Execute Unauthorized Code or Commands
Integrity: Modify Memory
Integrity: Modify Application Data
Access Control: Bypass Protection Mechanism
Potential Mitigations
Phase: Architecture and Design
Effectiveness: High
Description:
If feasible, the manufacturer should disable the JTAG interface or implement authentication and authorization for the JTAG interface. If authentication logic is added, it should be resistant to timing attacks. Security-sensitive data stored in registers, such as keys, etc. should be cleared when entering debug mode.
CVE References
- CVE-2019-18827
- chain: JTAG interface is not disabled (CWE-1191) during ROM code execution, introducing a race condition (CWE-362) to extract encryption keys