Building Cybersecurity into the supply chain is essential as threats mount

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The content of this post is solely the responsibility of the author.  AT&T does not adopt or endorse any of the views, positions, or information provided by the author in this article. 

The supply chain, already fragile in the USA, is at severe and significant risk of damage by cyberattacks. According to research analyzed by Forbes, supply chain attacks now account for a huge 62% of all commercial attacks, a clear indication of the scale of the challenge faced by the supply chain and the logistics industry as a whole. There are solutions out there, however, and the most simple of these concerns a simple upskilling of supply chain professionals to be aware of cybersecurity systems and threats. In an industry dominated by the need for trust, this is something that perhaps can come naturally for the supply chain.

Building trust and awareness

At the heart of a successful supply chain relationship is trust between partners. Building that trust, and securing high quality business partners, relies on a few factors. Cybersecurity experts and responsible officers will see some familiarity – due diligence, scrutiny over figures, and continuous monitoring. In simple terms, an effective framework of checking and rechecking work, monitored for compliance on all sides.

These factors are a key part of new federal cybersecurity rules, according to news agency Reuters. Among other measures are a requirement for companies to have rigorous control over system patching, and measures that would require cloud hosted services to identify foreign customers. These are simple but important steps, and give a hint to supply chain businesses as to what they should be doing; putting in measures to monitor, control, and enact compliance on cybersecurity threats. That being said, it can be the case that the software isn’t in place within individual businesses to ensure that level of control. The right tools, and the right personnel, is also essential.

The importance of software

Back in April, the UK’s National Cyber Security Centre released details of specific threats made by Russian actors against business infrastructure in the USA and UK. Highlighted in this were specific weaknesses in business systems, and that includes in hardware and software used by millions of businesses worldwide. The message is simple – even industry standard software and devices have their problems, and businesses have to keep track of that.

There are two arms to ensure this is completed. Firstly, the business should have a cybersecurity officer in place whose role it is to monitor current measures and ensure they are kept up to date. Secondly, budget and time must be allocated at an executive level firstly to promote networking between the business and cybersecurity firms, and between partner businesses to ensure that even cybersecurity measures are implemented across the chain.

Utilizing AI

There is something of a digital arms race when it comes to artificial intelligence. As ZDNet notes, the lack of clear regulation is providing a lot of leeway for malicious actors to innovate, but for businesses to act, too. While regulations are now coming in, it remains that there is a clear role for AI in prevention.

According to an expert interviewed by ZDNet in their profile of the current situation, digital threat hunters are already using sophisticated AI to look for patterns, patches and unusual actions on the network, and are then using these large data sets to join up the dots and provide reports to cyber security officers. Where the challenge arrives is in that weapons race; as AI models become more sophisticated and powerful, they will ‘hack’ faster than humans can. The defensive models need to stay caught up but will struggle with needing to act within regulatory guidelines. The key here will be in proactive regulation from the government, to enable businesses to deploy these measures with assurance as to their legality and safety. 

With the supply chain involving so many different partners, there are a wider number of wildcards that can potentially upset the balance of the system. However, businesses that are willing to take a proactive step forward and be an example within their own supply chain ecosystem stand to benefit. By building resilience into their own part of the process, and influencing partners to do the same, they can make serious inroads in fighting back against the overwhelming number of supply chain oriented cybersecurity threats.

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USN-6287-1: Go yaml vulnerabilities

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Simon Ferquel discovered that the Go yaml package incorrectly handled
certain YAML documents. If a user or an automated system were tricked
into opening a specially crafted input file, a remote attacker could
possibly use this issue to cause the system to crash, resulting in
a denial of service. (CVE-2021-4235)

It was discovered that the Go yaml package incorrectly handled
certain large YAML documents. If a user or an automated system were tricked
into opening a specially crafted input file, a remote attacker could
possibly use this issue to cause the system to crash, resulting in
a denial of service. (CVE-2022-3064)

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microcode_ctl-2.1-53.2.fc37

Read Time:9 Minute, 34 Second

FEDORA-2023-10d34be85a

Packages in this update:

microcode_ctl-2.1-53.2.fc37

Update description:

Update to upstream release 20230808
Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000171 up to 0x1000181;
Update of 06-55-04/0xb7 (SKX-D/SP/W/X H0/M0/M1/U0) microcode from revision 0x2006f05 up to 0x2007006;
Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x4003501 up to 0x4003604;
Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision 0x5003501 up to 0x5003604;
Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x7002601 up to 0x7002703;
Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000390 up to 0xd0003a5;
Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xba up to 0xbc;
Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode from revision 0xaa up to 0xac;
Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x2a up to 0x2c;
Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x44 up to 0x46;
Update of 06-8e-09/0xc0 (KBL-U/U 2+3e/Y H0/J1) microcode from revision 0xf2 up to 0xf4;
Update of 06-8e-09/0x10 (AML-Y 2+2 H0) microcode from revision 0xf2 up to 0xf4;
Update of 06-8e-0a/0xc0 (CFL-U 4+3e D0, KBL-R Y0) microcode from revision 0xf2 up to 0xf4;
Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xf2 up to 0xf4;
Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0) microcode from revision 0xf6 up to 0xf8;
Update of 06-8f-04/0x10 microcode from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-04) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-04) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-04) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-04) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-04) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-04) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-04) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-05) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-05/0x10 (SPR-HBM B1) microcode from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-05) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-05) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-05) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-05) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-05) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-06) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-06) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-06) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-06/0x10 microcode from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-06) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-06) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-06) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-07) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-07) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-07) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-07) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-08) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-08) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-08) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-08) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-08) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-08) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-08/0x10 (SPR-HBM B3) microcode from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision 0x2c up to 0x2e;
Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-97-02) from revision 0x2c up to 0x2e;
Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x2c up to 0x2e;
Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x2c up to 0x2e;
Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-97-05) from revision 0x2c up to 0x2e;
Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x2c up to 0x2e;
Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x2c up to 0x2e;
Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x2c up to 0x2e;
Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision 0x42a up to 0x42c;
Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in intel-ucode/06-9a-03) from revision 0x42a up to 0x42c;
Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in intel-ucode/06-9a-04) from revision 0x42a up to 0x42c;
Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x42a up to 0x42c;
Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision 0xf2 up to 0xf4;
Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) microcode from revision 0xf2 up to 0xf4;
Update of 06-9e-0b/0x02 (CFL-E/H/S B0) microcode from revision 0xf2 up to 0xf4;
Update of 06-9e-0c/0x22 (CFL-H/S/Xeon E P0) microcode from revision 0xf2 up to 0xf4;
Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode from revision 0xf8 up to 0xfa;
Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xf6 up to 0xf8;
Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xf6 up to 0xf8;
Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xf6 up to 0xf8;
Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xf6 up to 0xf8;
Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision 0xf6 up to 0xf8;
Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x58 up to 0x59;
Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x113 up to 0x119;
Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-02) from revision 0x2c up to 0x2e;
Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-02) from revision 0x2c up to 0x2e;
Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x2c up to 0x2e;
Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02) from revision 0x2c up to 0x2e;
Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-05) from revision 0x2c up to 0x2e;
Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-05) from revision 0x2c up to 0x2e;
Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05) from revision 0x2c up to 0x2e;
Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x2c up to 0x2e;
Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision 0x4112 up to 0x4119 (old pf 0xc0);
Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in intel-ucode/06-ba-02) from revision 0x4112 up to 0x4119 (old pf 0xc0);
Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in intel-ucode/06-ba-03) from revision 0x4112 up to 0x4119 (old pf 0xc0);
Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4112 up to 0x4119 (old pf 0xc0);
Update of 06-be-00/0x11 (ADL-N A0) microcode from revision 0x10 up to 0x11 (old pf 0x1).
Addresses CVE-2022-21216, CVE-2022-40982, CVE-2022-41804, CVE-2023-23908

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microcode_ctl-2.1-55.1.fc38

Read Time:9 Minute, 34 Second

FEDORA-2023-e1482687dd

Packages in this update:

microcode_ctl-2.1-55.1.fc38

Update description:

Update to upstream release 20230808
Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000171 up to 0x1000181;
Update of 06-55-04/0xb7 (SKX-D/SP/W/X H0/M0/M1/U0) microcode from revision 0x2006f05 up to 0x2007006;
Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x4003501 up to 0x4003604;
Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision 0x5003501 up to 0x5003604;
Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x7002601 up to 0x7002703;
Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000390 up to 0xd0003a5;
Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xba up to 0xbc;
Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode from revision 0xaa up to 0xac;
Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x2a up to 0x2c;
Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x44 up to 0x46;
Update of 06-8e-09/0xc0 (KBL-U/U 2+3e/Y H0/J1) microcode from revision 0xf2 up to 0xf4;
Update of 06-8e-09/0x10 (AML-Y 2+2 H0) microcode from revision 0xf2 up to 0xf4;
Update of 06-8e-0a/0xc0 (CFL-U 4+3e D0, KBL-R Y0) microcode from revision 0xf2 up to 0xf4;
Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xf2 up to 0xf4;
Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0) microcode from revision 0xf6 up to 0xf8;
Update of 06-8f-04/0x10 microcode from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-04) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-04) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-04) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-04) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-04) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-04) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-04) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-05) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-05/0x10 (SPR-HBM B1) microcode from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-05) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-05) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-05) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-05) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-05) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-06) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-06) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-06) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-06/0x10 microcode from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-06) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-06) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-06) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-07) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-07) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-07) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-07) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-08) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-08) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-08) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-08) from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-08) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-08) from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-8f-08/0x10 (SPR-HBM B3) microcode from revision 0x2c0001d1 up to 0x2c000271;
Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision 0x2b000461 up to 0x2b0004b1;
Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision 0x2c up to 0x2e;
Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-97-02) from revision 0x2c up to 0x2e;
Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x2c up to 0x2e;
Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x2c up to 0x2e;
Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-97-05) from revision 0x2c up to 0x2e;
Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x2c up to 0x2e;
Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x2c up to 0x2e;
Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x2c up to 0x2e;
Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision 0x42a up to 0x42c;
Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in intel-ucode/06-9a-03) from revision 0x42a up to 0x42c;
Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in intel-ucode/06-9a-04) from revision 0x42a up to 0x42c;
Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x42a up to 0x42c;
Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision 0xf2 up to 0xf4;
Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) microcode from revision 0xf2 up to 0xf4;
Update of 06-9e-0b/0x02 (CFL-E/H/S B0) microcode from revision 0xf2 up to 0xf4;
Update of 06-9e-0c/0x22 (CFL-H/S/Xeon E P0) microcode from revision 0xf2 up to 0xf4;
Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode from revision 0xf8 up to 0xfa;
Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xf6 up to 0xf8;
Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xf6 up to 0xf8;
Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xf6 up to 0xf8;
Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xf6 up to 0xf8;
Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision 0xf6 up to 0xf8;
Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x58 up to 0x59;
Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x113 up to 0x119;
Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-02) from revision 0x2c up to 0x2e;
Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-02) from revision 0x2c up to 0x2e;
Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x2c up to 0x2e;
Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02) from revision 0x2c up to 0x2e;
Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-05) from revision 0x2c up to 0x2e;
Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-05) from revision 0x2c up to 0x2e;
Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05) from revision 0x2c up to 0x2e;
Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x2c up to 0x2e;
Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision 0x4112 up to 0x4119 (old pf 0xc0);
Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in intel-ucode/06-ba-02) from revision 0x4112 up to 0x4119 (old pf 0xc0);
Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in intel-ucode/06-ba-03) from revision 0x4112 up to 0x4119 (old pf 0xc0);
Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4112 up to 0x4119 (old pf 0xc0);
Update of 06-be-00/0x11 (ADL-N A0) microcode from revision 0x10 up to 0x11 (old pf 0x1).
Addresses CVE-2022-21216, CVE-2022-40982, CVE-2022-41804, CVE-2023-23908

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